8-bit up counter simulation output.įigure 9. To view the changes in all the signals the out signal is expanded as in Figure 9.įigure 8. Figure 8 shows the simulation for the 8-bit up counter. Press “F” to fit all the signals in the screen. Finally, from the drop-down menus go to Run –> Run -All>. In the “Objects” window right-click anywhere and select Wave –> Signals in Region> this should add your main signals to the “wave” screen. ModelSim window with the “Simulate” layout. Also, note the “Objects” window and the signals it has.įigure 7. Note that a new tab called “Wave” was added to your right-hand-side, and another tab called “sim” to the left-hand-side.
The layout of the ModelSim main window should change from the “NoDesign” format, shown in Figure 1, to the “Simulate” format, shown in Figure 7. Then, right-click on the testbench file and select. In the “ Library” tab expand, which is the specified working directory for this project.
Modeltech modelsim code#
3 Simulate un-synthesized SystemVerilogĪfter preparing the Verilog code and the testbench and compiling both of them, it is now time to run the simulation and visualize the waveforms. SystemVerilog code for an 8-Bit Up Counter testbench. As an example, a testbench for the 8-bit up counter is shown in Figure 6.įigure 6. Follow the steps as in sections 2.2 and 2.3, and write your desired testing procedure. Fill in the fields as in section 2.1, while naming the file _TB.v. A “ Create Project File” window will open. To create a testbench, create a new file by right-clicking in the project tab then from the menu select New File…>. So to save your time, try to make sure that you are using synthesizable SystemVerilog from the beginning. Note: ModelSim will not check if the provided code is synthesizable or not, this is the task of the synthesis tool. If the file is clean, the file status will change to “ ✓” and a message in the transcript window saying “ # Compile of. Clicking on the message window will open a new window that has the errors description. If the file has any errors, the file status will change to “ X ” and a message in the transcript saying “ # Compile of. From the menu select, and note the Transcript window and the file status. 2.3 Compile the Verilog fileĪfter writing the code, go to the Project tab and right-click on the file in use. Note: Use detailed comments in your code – important for others reading your code, for yourself in the future, and for your grades. SystemVerilog code for an 8-Bit Up Counter. In this tutorial, as an example, an 8-Bit Simple up counter will be created as shown in Figure 5.įigure 5. The next step is to start writing SystemVerilog code in the text editor.
Left: The project tab shows the new file. This will open ModelSim’s text editor as shown in Figure 4-right.įigure 4. To start writing the SystemVerilog code right-click on the file and select Edit as shown in Figure 4-left. Now you will notice that the file was added to the project, and its status is “ ?”. Create a new SystemVerilog file 2.2 Write a SystemVerilog file Fill in the file name, which should reflect the function of the module, and select the type of the file to be SystemVerilog as shown in Figure 3-right. By selecting “Create New File”, a new widow named “Create Project File” will open. Project Location = Browse to the working directory created in section 1.1Īfter clicking “OK”, a new window will open to add a new item to the project as shown in Figure 3-left. In the Create Project window set the fields as follows and as shown in Figure 2: This will open a “Create Project” window. 2.1 Create a new projectįrom the drop-down menus go to New –> Project…>.
Modeltech modelsim how to#
The objective of this section is to learn how to create a new project, deal with ModelSim’s text editor, and compile the created code. ModelSim initial screen 2 Create and compile SystemVerilog modules ModelSim should open a window as in Figure 1.įigure 1. > source /CMC/scripts/mentor.modelsim.10.3.csh After sourcing the setup file, launch the tool.
Sourcing this file will take care of all the needed environment variables/licensing. In the working directory that you just created, source the provided setup file. 1.2 Source the setup file and run ModelSim Note: You will need to do this step for only the first time using the tool. Create a new working directory for ModelSim and name it, then descend into that directory using the following command lines: > mkdir ModelSim_ StudentNumber In your home directory, open a new shell. The objective of this section is to learn how to get the environment ready for the tool, take care of the licensing issues, and start the tool. 1 Environment Setup and starting ModelSim
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ModelSim is an HDL simulation software from Mentor Graphics. ~ Ajith S Ramani and Abdelrahman 10/2016 ~
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